FPGA Based Hardware Implementation of Image Filter With Dynamic Reconfiguration Architecture

Reconfigurable computing has been proposed for image and signal processing applications with various objectives, including high performance, flexibility, specialization, and most recently, adaptability. Reconfiguration is characterized by how fast the reconfiguration can occur and how many possible reconfigurations can be used and this feature is referred to as dynamic reconfiguration. For many image processing systems [5], it is possible to exploit variations in image signals to vary computation and memory requirements. In this paper, based on noise levels at a specific time instant, minimally sufficient hardware resources are dynamically allocated to meet the MDPP requirements of the application. These architectures can be characterized via a set of architectural parameters which can be determined experimentally. In this work, the analysis and hardware implementation of a dynamic reconfigurable unit based image filtering algorithm is described. This work is the first operational implementation of the reconfigurable architecture and its algorithm and is targeted to a Xilinx 600K Spartan-IIE FPGA to take advantage of computational specialization and parallelism. Our work has the capability to adapt the amount of computation performed and the amount of storage used at both a finetimescale (ms) and coarse-timescale (s) level. Experimental results show that the overall runtime of the image filter implementation on a Spartan-IIE FPGA, including bus overhead, is up to 400 times faster than a software implementation on a 2.8GHz Pentium processor.