Design And Implementation Of A Low Power Asynchronous Gps Baseband Processor

This thesis presents the design and implementation of a low-power asynchronous circuit for processing the digital component of the Global Positioning System (GPS) signal. The GPS signal structure is described and opportunities for applications of asynchronous design are presented. A selection of interesting circuit implementations exploiting these opportunities are presented and their efficiency and correctness are argued. The thesis continues with a description of how these circuits were implemented in silicon circuits and concludes with a comparison of power and performance between this implementation and other contemporary GPS systems. This comparison finds the 1.4 mW GPS processor described to use less energy per position update than any published processor.

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