Exploiting on-chip inductance in high speed clock distribution networks
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[1] Keith A. Jenkins,et al. Design guidelines for short, medium, and long on-chip interconnections , 1996 .
[2] Masakazu Shoji,et al. High-Speed Digital Circuits , 1996 .
[3] Keith A. Jenkins,et al. When are transmission-line effects important for on-chip interconnections? , 1997 .
[4] Denis B. Jarvis. The Effects of Interconnections on High-Speed Logic Circuits , 1963, IEEE Trans. Electron. Comput..
[5] Eby G. Friedman,et al. Repeater design to reduce delay and power in resistive interconnect , 1998 .
[6] Mark A. Franklin,et al. Optimum buffer circuits for driving long uniform lines , 1991 .
[7] Robert H. Dennard,et al. Modeling and characterization of long on-chip interconnections for high-performance microprocessors , 1995, IBM Journal of Research and Development.
[8] D. A. Priore. Inductance on silicon for sub-micron CMOS VLSI , 1993, Symposium 1993 on VLSI Circuits.
[9] Alina Deutsch,et al. Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[10] Yehea I. Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[11] Charles J. Alpert,et al. Wire segmenting for improved buffer insertion , 1997, DAC.
[12] Larry Pileggi,et al. Coping with RC(L) interconnect design headaches , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[13] Sharad Mehrotra,et al. Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[14] Eby G. Friedman,et al. Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load , 1996 .
[15] Srinivasa Vemuru,et al. Short-circuit power dissipation estimation for cmos logic gates , 1994 .
[16] J. Torres,et al. Advanced copper interconnections for silicon CMOS technologies , 1995 .
[17] Jacob K. White,et al. Layout techniques for minimizing on-chip interconnect self-inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[18] Allen Taflove,et al. FD-TD modeling of digital signal propagation in 3-D circuits with passive and active loads , 1994 .
[19] J.D. Meindl,et al. Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.
[20] Gerard V. Kopcsay,et al. High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..
[21] Lawrence T. Pileggi. Coping with RC(L) interconnect design headaches , 1995, ICCAD.
[22] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[23] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[24] W. R. Eisenstadt,et al. High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .