An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders
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Yi Wu | Weikang Qian | You Li | Yuan Gao | Xiangxuan Ge | You Li | Yi Wu | Weikang Qian | Yuan Gao | X. Ge
[1] Yi Wu,et al. An efficient method for multi-level approximate logic synthesis under error rate constraint , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[2] Fabrizio Lombardi,et al. An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.
[3] Fabrizio Lombardi,et al. Inexact designs for approximate low power addition by cell replacement , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[4] Muhammad Shafique,et al. A low latency generic accuracy configurable adder , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[5] Luis Ceze,et al. Neural Acceleration for General-Purpose Approximate Programs , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[6] Gang Wang,et al. Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.
[7] Olivier Temam,et al. Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).
[8] Sergio Bampi,et al. Approximation-aware Multi-Level Cells STT-RAM cache architecture , 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).
[9] Ronald L. Rivest,et al. Introduction to Algorithms, 3rd Edition , 2009 .
[10] Peter J. Varman,et al. High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[11] Li Li,et al. On error modeling and analysis of approximate adders , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[12] Puneet Gupta,et al. Trading Accuracy for Power with an Underdesigned Multiplier Architecture , 2011, 2011 24th Internatioal Conference on VLSI Design.
[13] Paolo Ienne,et al. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.
[14] Muhammad Shafique,et al. Probabilistic Error Modeling for Approximate Adders , 2017, IEEE Transactions on Computers.
[15] Muhammad Shafique,et al. An area-efficient consolidated configurable error correction for approximate hardware accelerators , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[16] Muhammad Shafique,et al. Thermal optimization using adaptive approximate computing for video coding , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[17] Muhammad Shafique,et al. QuAd: Design and analysis of Quality-area optimal Low-Latency approximate Adders , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).
[18] Kaushik Roy,et al. Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[19] Muhammad Shafique,et al. Statistical error analysis for low power approximate adders , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).
[20] Kaushik Roy,et al. Quality programmable vector processors for approximate computing , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[21] Semeen Rehman,et al. Architectural-space exploration of approximate multipliers , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[22] Kaushik Roy,et al. Design of power-efficient approximate multipliers for approximate artificial neural networks , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[23] Rakesh Kumar,et al. On reconfiguration-oriented approximate adder design and its application , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[24] Andrew B. Kahng,et al. Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.
[25] Muhammad Shafique,et al. Invited: Cross-layer approximate computing: From logic to architectures , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[26] Weikang Qian,et al. A new approximate adder with low relative error and correct sign calculation , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[27] Jie Han,et al. Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).
[28] Caro Lucas,et al. Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[29] Andreas Gerstlauer,et al. Statistical quality modeling of approximate hardware , 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).
[30] Kaushik Roy,et al. Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[31] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[32] Kiat Seng Yeo,et al. Low-power high-speed multiplier for error-tolerant application , 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).
[33] Yong Zhang,et al. An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[34] Lukás Sekanina,et al. Evolutionary Approach to Approximate Digital Circuits Design , 2015, IEEE Transactions on Evolutionary Computation.