Design Space Motion Estimation Architectures

In this chapter motion estimation architectures are evaluated for the requirements of the visual (video) part of the MPEG-4 standard. Due to the very complex nature of the design space for motion estimation VLSI architectures, there are numerous VLSI architectures and design trade-offs. Proper consideration of these trade-offs can lead to an optimal VLSI architecture design for a selected motion estimation (ME) algorithm or a number of selected motion estimation algorithms under particular application constraints. The aim of this chapter is to evaluate block-matching motion estimation algorithms from a hardware point of view for MPEG-4. This is in contrast to the previous chapter where the block-matching algorithms were evaluated in terms of number of operations and memory bandwidth for software implementation on a programmable processor. It will be shown that the commonly used complexity metric of the number of operations for a processor implementation is not suitable for VLSI implementations.

[1]  Liang-Gee Chen,et al.  An efficient and simple VLSI tree architecture for motion estimation algorithms , 1993, IEEE Trans. Signal Process..

[2]  Chen-Yi Lee,et al.  Buffer size optimization for full-search block matching algorithms , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Fausto Pellandini,et al.  BIT-SERIAL PARALLEL PROCESSING VLSI ARCHITECTURE FOR A BLOCK MATCHING MOTION ESTIMATION ALGORITHM , 1994 .

[4]  K. J. Ray Liu,et al.  Algorithm-based low-power transform coding architectures , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[5]  Masahiko Yoshimoto,et al.  A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search , 1995 .

[6]  F. Catthoor,et al.  A Memory Efficient, Programmable Multi-Processor Architecture for Real-Time Motion Estimation Type Algorithms , 1995 .

[7]  P. Lakamsani.  An architecture for enhanced three step search generalized for hierarchical motion estimation algorithms , 1997 .

[8]  Teresa H. Meng,et al.  Parallel array architectures for motion estimation , 1991, Proceedings of the International Conference on Application Specific Array Processors.

[9]  Walter Stechele,et al.  VLSI architecture for variable-block-size motion estimation with luminance correction , 1997, Optics & Photonics.

[10]  Chaitali Chakrabarti,et al.  Architectures for hierarchical and other block matching algorithms , 1995, IEEE Trans. Circuits Syst. Video Technol..

[11]  Vijay K. Madisetti.  VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis , 1995 .

[12]  Chen-Mie Wu,et al.  A VLSI motion estimator for video image compression , 1993 .

[13]  Nicolas Demassieux,et al.  Real-time architecture for large displacements estimation , 1994, Other Conferences.

[14]  Moon Key Lee,et al.  Flexible VLSI architecture of full search motion estimation for video applications , 1994 .

[15]  Tobias G. Noll,et al.  A flexible motion estimation chip for variable size block matching , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[16]  Sethuraman Panchanathan,et al.  Fast motion estimation using feature extraction and XOR operations , 1998, Electronic Imaging.

[17]  Luc De Vos,et al.  VLSI architectures for the hierarchical block-matching algorithm for HDTV applications , 1990, VCIP.

[18]  Ruby B. Lee,et al.  Algorithmic and architectural enhancements for real-time MPEG-1 decoding on a general purpose RISC workstation , 1995, IEEE Trans. Circuits Syst. Video Technol..

[19]  Hugo De Man,et al.  The systematic design of a motion estimation array architecture , 1991, Proceedings of the International Conference on Application Specific Array Processors.

[20]  Y.-K. Lai,et al.  A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation , 1997, Proceedings of International Conference on Image Processing.

[21]  Ming-Ting Sun.  8 - Algorithms and VLSI Architectures for Motion Estimation , 1993 .

[22]  W. Kever,et al.  HP's PA7100LC: a low-cost superscalar PA-RISC processor , 1993, Digest of Papers. Compcon Spring.

[23]  A. Torielli,et al.  Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[24]  Andreas Graf,et al.  A RISC controlled motion estimation processor for MPEG-2 and HDTV encoding , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[25]  Chin-Liang Wang,et al.  A high-throughput, flexible VLSI architecture for motion estimation , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[26]  Jef L. van Meerbergen,et al.  Optimization of address generator hardware , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[27]  Clifford Liem,et al.  Retargetable Compilers for Embedded Core Processors , 1997, Springer US.

[28]  Chen-Yi Lee,et al.  Semi-systolic array based motion estimation processor design , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[29]  Michael Stegherr,et al.  Parameterizable VLSI architectures for the full-search block-matching algorithm , 1989 .

[30]  Ming Lei Liou,et al.  Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm , 1997, J. VLSI Signal Process..

[31]  Y. Iida,et al.  A cost effective motion estimation processor LSI using a simple and efficient algorithm , 1995 .

[32]  Konstantinos Konstantinides,et al.  Image and video compression standards , 1995 .

[33]  Y. Tashiro,et al.  A real-time motion estimation and compensation LSI with wide-search range for MPEG2 video encoding , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[34]  Santanu Dutta,et al.  A flexible parallel architecture adapted to block-matching motion-estimation algorithms , 1996, IEEE Trans. Circuits Syst. Video Technol..

[35]  Ed F. Deprettere,et al.  Parallel architecture for a pel-recursive motion estimation algorithm , 1992, CompEuro 1992 Proceedings Computer Systems and Software Engineering.

[36]  Anantha Chandrakasan,et al.  A binary block matching architecture with reduced power consumption and silicon area requirement , 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

[37]  Hsueh-Ming Hang,et al.  Motion Estimation for Video Coding Standards , 1997, J. VLSI Signal Process..

[38]  Wei Ding,et al.  Standard-based software-only video conferencing codec on Ultra SPARC , 1998, Electronic Imaging.

[39]  Peter Pirsch,et al.  Array architectures for block matching algorithms , 1989 .

[40]  Sethuraman Panchanathan,et al.  Motion estimation architecture for video compression , 1993 .

[41]  A. Boxer.  Where buses cannot go , 1995 .

[42]  T. G. Noll,et al.  A cascadable 200 GOPS motion estimation chip for HDTV applications , 1996, Proceedings of Custom Integrated Circuits Conference.

[43]  Masahiko Yoshimoto,et al.  A half-pel precision motion estimation processor for NTSC-resolution video , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[44]  Serge Vernalde,et al.  Highly scalable parallel parametrizable architecture of the motion estimator , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[45]  Choong Woong Lee,et al.  A VLSI chip for motion estimation of HDTV signals , 1994 .

[46]  M. Ernst,et al.  System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation , 1993, J. VLSI Signal Process..

[47]  Jinwoong Kim,et al.  Field- and frame-based motion estimator with a very flexible search range , 1996, Other Conferences.

[48]  Chen-Yi Lee,et al.  A parallel bit-level maximum/minimum selector for digital and video signal processing , 1994 .

[49]  Xiaoming Li,et al.  A locally quadratic model of the motion estimation error criterion function and its application to subpixel interpolations , 1996, IEEE Trans. Circuits Syst. Video Technol..

[50]  Amanda Richardson,et al.  STi 3220 motion estimation processor , 1993, Microprocess. Microsystems.

[51]  Ming Lei Liou,et al.  Design Trade-Offs for Real-Time Block Matching Motion Estimation Algorithms , 1995, ACCV.

[52]  Yutaka Yokoyama,et al.  An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[53]  Yeong-Kang Lai,et al.  A flexible data-interlacing architecture for full-search block-matching algorithm , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[54]  Hsueh-Ming Hang,et al.  A comparison of block-matching algorithms mapped to systolic-array implementation , 1997, IEEE Trans. Circuits Syst. Video Technol..

[55]  Chi-Ying Tsui,et al.  Low power motion estimation design using adaptive pixel truncation , 1997, ISLPED '97.

[56]  R. Neogi,et al.  Parallel programmable algorithm and architecture for real-time motion estimation of various video applications , 1995 .

[57]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[58]  Chaur-Heh Hsieh,et al.  VLSI architecture for block-matching motion estimation algorithm , 1992, IEEE Trans. Circuits Syst. Video Technol..

[59]  Sau-Gee Chen.  An area/time-efficient motion estimation micro core , 1993 .

[60]  Gihyun Jung,et al.  A fast motion estimator for real-time system , 1997 .

[61]  Shyang Chang,et al.  Zero waiting-cycle hierarchical block matching algorithm and its array architectures , 1994, IEEE Trans. Circuits Syst. Video Technol..

[62]  Jürgen Becker,et al.  A novel sequencer hardware for application specific computing , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[63]  Walter Stechele,et al.  A flexible VLSI architecture for variable block size segment matching with luminance correction , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[64]  B. Canfield,et al.  A programmable motion estimation processor for full search block matching , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[65]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[66]  Ya-Qin Zhang,et al.  A fast hierarchical motion-compensation scheme for video coding using block feature matching , 1996, IEEE Trans. Circuits Syst. Video Technol..

[67]  Ben Cohen.  VHDL answers to frequently asked questions , 1996 .

[68]  Konstantinos Konstantinides,et al.  Hardware for Motion Estimation , 1995 .

[69]  Konstantinos Konstantinides,et al.  Low-complexity algorithm and architecture for block-based motion estimation via one-bit transforms , 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

[70]  Sven Bauer,et al.  The MPEG-4 video coding standard-a VLSI point of view , 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

[71]  Ruby B. Lee.  Accelerating multimedia with enhanced microprocessors , 1995, IEEE Micro.

[72]  Keikichi Tamaru,et al.  A memory efficient array architecture for full-search block matching algorithm , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[73]  Chen-Yi Lee,et al.  An Efficient VLSI Architecture for Full-Search Block Matching Algorithms , 1997, J. VLSI Signal Process..

[74]  Ming-Ting Sun,et al.  A family of vlsi designs for the motion compensation block-matching algorithm , 1989 .

[75]  Matthias Schöbinger,et al.  VLSI architecture for a flexible block matching processor , 1995, IEEE Trans. Circuits Syst. Video Technol..

[76]  Hae-Kwan Jung,et al.  A VLSI architecture for the alternative subsampling-based block matching algorithm , 1995 .

[77]  Sung Bum Pan,et al.  VLSI architectures for block matching algorithms using systolic arrays , 1996, IEEE Trans. Circuits Syst. Video Technol..

[78]  Yu Hen Hu,et al.  A high-throughput modular architecture for three-step search block matching motion estimation , 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

[79]  Yoshitsugu Araki,et al.  New address-generation-unit architecture for video signal processing , 1991, Other Conferences.

[80]  Jean-Didier Legat,et al.  Parallel processor for motion estimation , 1996, Other Conferences.

[81]  Andrew Wolfe,et al.  A methodology to evaluate memory architecture design tradeoffs for video signal processors , 1998, IEEE Trans. Circuits Syst. Video Technol..

[82]  Heung-Kyu Lee,et al.  Block-matching criterion for efficient VLSI implementation of motion estimation , 1996 .

[83]  David A. Carlson,et al.  Multimedia extensions for a 550-MHz RISC microprocessor , 1997 .

[84]  Yu Hen Hu,et al.  A novel modular systolic array architecture for full-search block matching motion estimation , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[85]  Keikichi Tamaru,et al.  A memory efficient array architecture for real-time motion estimation , 1997, Proceedings 11th International Parallel Processing Symposium.

[86]  Shih-Yu Huang,et al.  Very large scale integration (VLSI) architecture for motion estimation and vector quantization , 1994, Other Conferences.

[87]  A. Artieri,et al.  A dedicated circuit for real time motion estimation , 1991, Euro ASIC '91.

[88]  P. Faraboschi,et al.  A VLSI architecture for hierarchical motion estimation , 1995 .

[89]  Yu Hen Hu,et al.  A novel modular systolic array architecture for full-search block matching motion estimation , 1995, IEEE Trans. Circuits Syst. Video Technol..

[90]  Hsueh-Ming Hang,et al.  Comparison of block-matching algorithms for VLSI implementation , 1996, Other Conferences.

[91]  Konstantinos Konstantinides,et al.  Low-complexity block-based motion estimation via one-bit transforms , 1997, IEEE Trans. Circuits Syst. Video Technol..

[92]  Hugo De Man,et al.  Architectural exploration and optimization for counter based hardware address generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[93]  Liang-Gee Chen,et al.  Parallel architectures for 3-step hierarchical search block-matching algorithm , 1994, IEEE Trans. Circuits Syst. Video Technol..

[94]  Liang-Gee Chen,et al.  A new block-matching criterion for motion estimation and its implementation , 1995, IEEE Trans. Circuits Syst. Video Technol..

[95]  Srinivas Devadas,et al.  Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures , 1997, Des. Autom. Embed. Syst..

[96]  Chein-Wei Jen,et al.  Scalable array architecture design for full search block matching , 1995, IEEE Trans. Circuits Syst. Video Technol..