Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (fs/2) and quarter-rate (fs/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5× savings in digital power consumption for low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.

[1]  Amin Nassar,et al.  Power efficient polyphase comb decimation filters for ΣΔ modulators in multi-rate digital receivers , 2009, 2009 European Conference on Circuit Theory and Design.

[2]  Koichi Hamashita,et al.  LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators , 2010, IEEE Journal of Solid-State Circuits.

[3]  David J. Allstot,et al.  A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC. , 2007 .

[4]  Un-Ku Moon,et al.  Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection , 2000 .

[5]  Paulo S. R. Diniz,et al.  Adaptive Filtering: Algorithms and Practical Implementation , 1997 .

[6]  K. Muhammad,et al.  A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels , 2000, IEEE Journal of Solid-State Circuits.

[7]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[8]  L.J. Breems,et al.  Digital Calibration of a Continuous-Time Cascaded ΣΔ Modulator based on Variance Derivative Estimation , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[9]  David J. Allstot,et al.  Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems , 2011, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[10]  Alan V. Oppenheim,et al.  Discrete-time Signal Processing. Vol.2 , 2001 .

[11]  Un-Ku Moon,et al.  An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS , 2010, IEEE Journal of Solid-State Circuits.

[12]  Gert Cauwenberghs,et al.  Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration , 2000 .

[13]  Boris Murmann Digitally Assisted Analog Circuits , 2006, IEEE Micro.