New dynamic flip-flops for high-speed dual-modulus prescaler
暂无分享,去创建一个
Shen-Iuan Liu | Ching-Yuan Yang | Guang-Kaai Dehng | June-Ming Hsu | Shen-Iuan Liu | Ching-Yuan Yang | G. Dehng | June-Ming Hsu
[1] Qiuting Huang,et al. An 800-MHz 1-/spl mu/m CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops , 1996 .
[2] Byungsoo Chang,et al. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .
[3] Qiuting Huang,et al. 1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 /spl mu/m CMOS prescalers , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
[4] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .
[5] P. Larsson. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler , 1996 .
[6] T. Kwasniewski,et al. CMOS high-speed dual-modulus frequency divider for RF frequency synthesis , 1995 .
[7] Patrik Larsson. Skew safety and logic flexibility in a true single phase clocked system , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.
[8] Qiuting Huang,et al. Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks , 1996 .
[9] Jan Craninckx,et al. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .