Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study

This work has been partially supported by a collaboration agreement between Thales Research and the Barcelona Supercomputing Center, and the European Research Council (ERC) under the EU’s Horizon 2020 research and innovation programme (grant agreement No. 772773). MINECO partially supported Jaume Abella under Ramon y Cajal postdoctoral fellowship (RYC2013-14717).

[1]  Jan Reineke,et al.  Embedded systems: Many cores — Many problems , 2012, 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12).

[2]  Denny Marx,et al.  Non-Intrusive Tracing at First Instruction , 2015 .

[3]  Jason G. Tong,et al.  Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison , 2008, J. Comput..

[4]  Mikel Azkarate-askasua,et al.  WCET analysis methods: Pitfalls and challenges on their trustworthiness , 2015, 10th IEEE International Symposium on Industrial Embedded Systems (SIES).

[5]  Irune Agirre,et al.  Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis , 2016, WCET.

[6]  Rajendra Patel,et al.  A Survey of Embedded Software Profiling Methodologies , 2011, ArXiv.

[7]  Tullio Vardanega,et al.  Resource usage templates and signatures for COTS multicore processors , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  Francisco J. Cazorla,et al.  On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments , 2012, TACO.

[9]  Alexander Weiss,et al.  Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs , 2016, WCET.

[10]  Reinhold Heckmann,et al.  Verifying safety-critical timing and memory-usage properties of embedded software by abstract interpretation , 2005, Design, Automation and Test in Europe.

[11]  Sylvain Girbal,et al.  A complete toolchain for an interference-free deployment of avionic applications on multi-core systems , 2015, 2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC).

[12]  Jan Reineke,et al.  Challenges for Timing Analysis of Multi-Core Architectures , 2017 .

[13]  Henrik Theiling,et al.  Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement , 2014, 2014 26th Euromicro Conference on Real-Time Systems.

[14]  R. Wilhelm Mixed Feelings About Mixed Criticality , 2018 .

[15]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[16]  Raimund Kirner,et al.  Obstacles in Worst-Case Execution Time Analysis , 2008, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC).

[17]  Tullio Vardanega,et al.  ON THE INDUSTRIAL FITNESS OF WCET ANALYSIS , 2011 .

[18]  Vincent Nélis,et al.  An Analysis of the Impact of Bus Contention on the WCET in Multicores , 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

[19]  Francisco J. Cazorla,et al.  MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding , 2017, Ada-Europe.

[20]  Mikael Sjödin,et al.  Bandwidth measurement using performance counters for predictable multicore software , 2012, Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation (ETFA 2012).

[21]  Daniel Kästner,et al.  TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis , 2019, WCET.

[22]  Francisco J. Cazorla,et al.  Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP) , 2020, 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[23]  Daniel Gracia Pérez,et al.  Studying co-running avionic real-time applications on multi-core COTS architectures , 2014 .

[24]  Lui Sha,et al.  MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms , 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[25]  Reinhard Wilhelm,et al.  Mixed Feelings About Mixed Criticality (Invited Paper) , 2018, Worst-Case Execution Time Analysis.

[26]  Guillem Bernat,et al.  Hybrid measurement-based WCET analysis at the source level using object-level traces , 2010, WCET.

[27]  Francisco J. Cazorla,et al.  Modelling multicore contention on the AURIXTM TC27x , 2018, DAC.

[28]  Michael Paulitsch,et al.  Leveraging Multi-core Computing Architectures in Avionics , 2012, 2012 Ninth European Dependable Computing Conference.

[29]  Alan Burns,et al.  Guest Editorial: A Review of Worst-Case Execution-Time Analysis , 2000, Real-Time Systems.

[30]  Francisco J. Cazorla,et al.  High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V , 2018, IEEE Micro.

[31]  Tullio Vardanega,et al.  Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration , 2017, IEEE Transactions on Computers.

[32]  Alexander Weiss,et al.  Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation , 2015, WCET.

[33]  Francisco J. Cazorla,et al.  ePAPI: Performance Application Programming Interface for Embedded Platforms , 2019, WCET.

[34]  Jack J. Dongarra,et al.  A Portable Programming Interface for Performance Evaluation on Modern Processors , 2000, Int. J. High Perform. Comput. Appl..

[35]  Sylvain Girbal,et al.  Deterministic platform software for hard real-time systems using multi-core COTS , 2015, 2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC).

[36]  Thomas G. Baker Lessons Learned Integrating COTS into Systems , 2002, ICCBSS.