Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic
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[1] Nikolaos G. Bartzoudis,et al. Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded Microprocessors , 2008, 2008 14th IEEE International On-Line Testing Symposium.
[2] Matteo Sonza Reorda,et al. Exploiting the debug interface to support on-line test of control flow errors , 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).
[3] Raimund Ubar,et al. Constraint-based test pattern generation at the Register-Transfer Level , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.
[4] Janusz Rajski,et al. Test responses compaction in accumulators with rotate carry adders , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Constantin Halatsis,et al. R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[6] S.K. Mohideen,et al. Design of Built in Self Test Asynchronous Micropipeline using Double Edge Triggered D Flip Flop , 2005, 2005 Annual IEEE India Conference - Indicon.
[7] Jens Sparsø,et al. Principles of Asynchronous Circuit Design , 2001 .
[8] Alexandre Yakovlev,et al. On-line testing of globally asynchronous circuits , 2005, 11th IEEE International On-Line Testing Symposium.
[9] Amardeep Singh. Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing , 2003, VLSI.
[10] Dimitris Gizopoulos,et al. An Input Vector Monitoring Concurrent BIST scheme exploiting “X” values , 2009, 2009 15th IEEE International On-Line Testing Symposium.
[11] Cristian Constantinescu,et al. Impact of deep submicron technology on dependability of VLSI circuits , 2002, Proceedings International Conference on Dependable Systems and Networks.
[12] Alexandre Yakovlev,et al. FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities , 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.
[13] Ivan E. Sutherland,et al. Micropipelines , 1989, Commun. ACM.
[14] Jörg Henkel,et al. Transparent structural online test for reconfigurable systems , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).
[15] Jens Sparsø,et al. Asynchronous circuit design - A tutorial , 2001 .
[16] Themistoklis Haniotakis,et al. An efficient comparative concurrent Built-In Self-Test technique , 1995, Proceedings of the Fourth Asian Test Symposium.
[17] Xin Yuan,et al. Automated synthesis of a multiple-sequence test generator using 2-D LFSR , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).
[18] Constantin Halatsis,et al. An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set , 2008, IEEE Transactions on Computers.
[19] Stephen B. Furber,et al. Built-in self-testing of micropipelines , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[20] Shai Rotem,et al. CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).
[21] Felipe Maia Galvão França,et al. A BIST scheme for asynchronous logic , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).
[22] Ioannis Voyiatzis. Input vector monitoring on line concurrent BIST based on multilevel decoding logic , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[24] Yiorgos Makris,et al. Duplication-based concurrent error detection in asynchronous circuits: shortcomings and remedies , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..
[25] Kewal K. Saluja,et al. A concurrent testing technique for digital circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[26] Carol Q. Tong,et al. Built-in current self-testing scheme (BICST) for CMOS logic circuits , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.
[27] Markus Ferringer. Conversion of two- to four-phase delay-insensitive asynchronous circuits , 2011, 2011 IEEE EUROCON - International Conference on Computer as a Tool.
[28] Scott Hauck,et al. Asynchronous design methodologies: an overview , 1995, Proc. IEEE.
[29] Matteo Sonza Reorda,et al. An on-line fault detection technique based on embedded debug features , 2010, 2010 IEEE 16th International On-Line Testing Symposium.
[30] Edward J. McCluskey,et al. Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[31] Emmanuel Simeu,et al. A robust fault detection scheme for concurrent testing of linear digital systems , 2001, Proceedings Seventh International On-Line Testing Workshop.
[32] Kenneth Y. Yun,et al. Practical advances in asynchronous design and in asynchronous/synchronous interfaces , 1999, DAC '99.
[33] Steve Furber,et al. Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .
[34] William B. Toms,et al. Synthesising heterogeneously encoded systems , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).
[35] Andreas Steininger,et al. Dealing with dormant faults in an embedded fault-tolerant computer system , 2003, IEEE Trans. Reliab..
[36] Michael Gössel,et al. Concurrent checking with split-parity codes , 2009, 2009 15th IEEE International On-Line Testing Symposium.
[37] Michael Nicolaidis,et al. Self-exercising checkers for unified built-in self-test (UBIST) , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[38] Thomas W. Williams,et al. Design of compactors for signature-analyzers in built-in self-test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[39] Ondrej Novák,et al. Test-per-clock testing of the circuits with scan , 2001, Proceedings Seventh International On-Line Testing Workshop.
[40] Richard W. Hamming,et al. Error detecting and error correcting codes , 1950 .
[41] Yervant Zorian,et al. On-Line Testing for VLSI—A Compendium of Approaches , 1998, J. Electron. Test..
[42] Constantin Halatsis,et al. A low-cost concurrent BIST scheme for increased dependability , 2005, IEEE Transactions on Dependable and Secure Computing.
[43] Andreas Steininger,et al. Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.
[44] Dieter Fuhrmann,et al. Logical Effort Designing Fast Cmos Circuits , 2016 .
[45] Rolf Kraemer,et al. On-line testing of bundled-data asynchronous handshake protocols , 2010, 2010 IEEE 16th International On-Line Testing Symposium.
[46] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[47] Steven M. Nowick,et al. Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).
[48] Michael Nicolaidis,et al. Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.
[49] Markus Ferringer,et al. Conversion and interfacing techniques for asynchronous circuits , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
[50] H. Kopetz,et al. Dependability: Basic Concepts and Terminology , 1992, Dependable Computing and Fault-Tolerant Systems.
[51] Dimitris Gizopoulos,et al. Effective software-based self-test strategies for on-line periodic testing of embedded processors , 2005 .
[52] Deepali Koppad,et al. BIST for strongly-indicating asynchronous circuits , 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).
[53] F. J. te Beest,et al. Full scan testing of handshake circuits , 2003 .