Power Optimization of Communication System Using Clock Gating Technique

A power optimized communication system is proposed in this paper with clock gating technique. The encoder decoder block and the converter circuits are designed using clock gating for power optimization without degrading the system performance. Unwanted switching activities can be much reduced by using clock gating techniques and power saving can be done. Negative latch has been used to generate the gated clock which feeds into various blocks. The RTL view of the communication system with gated clock is also generated for implementation in hardware. We have used two clocks of frequencies 20MHz and 200MHz. For these frequencies, the hierarchy total power is reduced by 68.27%, the logic power is reduced by 53.33%, the signal power is reduced by 75.67% and the clock domain and on-chip powers are same as it is in the system without using gated clock. Verilog HDL has been used to implement the various blocks and simulation done using ModelSim 10.3c. RTL implementation has been done using Xilinx ISE suite 13.4.