Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques

FPGAs, as the most popular reconfigurable fabrics, have dramatically increased their computing capacity in the past years. Taking Xilinx FPGAs for example, the capacity of logic cells in Vertex-7 [8] has $100 \times $ increase than Vertex-4 [7], while the memory capacity has only $10 \times $ increase. The on-chip memory resources of modern FPGAs are scarce and inflexible (as they are located at certain positions). However, recent data-intensive tasks (e.g., machine learning and big-data applications) devote most of their processing time to I/O and data manipulation, leading to a large amount of memory access and data movement [4]. The limited on-chip memory resources in FPGAs restrict their ability to deal with data-intensive tasks in the new era. In addition, the configurable logics and interconnections, which are the main building blocks of modern FPGAs [5], cannot change their primary functionalities (for example, interconnections cannot implement logics), which also limits the flexibility of FPGAs when dealing with different applications.