Simd isa extensions: tradeoff between power consumption and performance on a superscalar processor

Preface The limits imposed by power consumption are becoming an issue in most areas of computing. The need to limit power consumption is readily apparent in the case of portable and mobile computer platforms — the laptop and the cell phone being the most common examples. But the need to limit power in other computer settings is becoming important too. This workshop is the third in a series of workshops and tutorials designed to bring together researchers in the area of architecture-power trade-offs and provide a forum for them to discuss their preliminary ideas. It helped raise the awareness of the architecture community to concerns about power issues. This workshop was followed by a tutorial, the Cool Chips Tutorial at MICRO32 in Haifa, Israel. It assembled a group of speakers from leading microprocessor companies to give presentations on what they consider to be their critical low power issues now and in the future, and some possible solutions to these problems. Abstract This paper discusses early results from a project called Morph where the goal is to develop a microarchitecture that can adapt its intrinsic performance dynamically. By observing that power dissipation is, to a first approximation , proportional to a power of the performance, reducing the performance characteristics thus reduces the power even faster, resulting in greatly improved performance/ watt characteristics. These techniques are largely independent of other techniques, such as voltage scaling, and as such add an extra runtime " gear " which a real embedded system may manipulate. In addition to the microarchitecture work, the paper also briefly discusses the driving application to be used in its evaluation, namely planetary rovers, and a discussion of some of the runtime software considerations that will be necessary to work through to make the " gear-changing " a usable piece of technology to real applications. 1.0 Introduction Many embedded systems go through long periods of time where only a low level of compute performance is needed, followed by periods where performance needs peak. Current high performance microprocessors, however, are designed to meet these peak needs with microarchitectures that have fixed characteristics , and which provide much lower MIPS per watt measures than simpler, but less powerful CPUs. Thus, ignoring the potential from voltage scaling, the only " knob " that an embedded system can twist to lower power in less performance demanding time periods is clock scaling. Unfortunately, lowering the clock …

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