STOCHASTIC MULTILEVEL INTERCONNECT MODELING AND OPTIMIZATION

Clock frequency, power consumption, and chip size are largely determined by the wiring requirements of a VLSI system [1, 2, 3]. It is, therefore, imperative to gain thorough understanding of wiring requirements for present and projected gigascale integrated (GSI) systems. It has been shown that optimized logic networks have certain collective properties that can be described with Rent’s Rule. Using this well-established empirical relationship as a starting point, a wire length distribution is rigorously derived to enable first order estimation of the local, semi-global, and global wiring requirements for GSI random logic networks. Applications to critical path modeling, power dissipation modeling, and die size estimation are explored. Finally, this chapter will conclude with an n-tier multilevel interconnect optimization that uses these models to help guide the design of advanced multilevel interconnect architectures for gigascale integration (GSI).

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