Statistical modeling of metastability in ADC-based serial I/O receivers
暂无分享,去创建一个
[1] Thomas Krause,et al. A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] Christer Svensson,et al. Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters , 2001 .
[3] Samuel Palermo,et al. Embedded equalization for ADC-based serial I/O receivers , 2011, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.
[4] Robert W. Brodersen,et al. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .