Interconnect delay testings of designs on programmable logic devices

Very thorough interconnect delay testing technique for designs implemented on programmable logic devices, such as FPGAs, is presented (application-dependent test). The presented technique achieves 1) 100% robust path delay coverage on all the paths in the design, 2) 100% transition fault coverage, and 3) 100% TARO coverage, transition to all reachable primary outputs. The required number of test configurations is two or four depending on the structure of the design. An algorithmic approach to generate the test vectors and configurations is presented.

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