An investigation of the intrinsic delay (speed limit) in MTL/I2L

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of today's MTL/I2L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.

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