Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- $\kappa$ Gate Dielectric

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.

[1]  W. Hawkins,et al.  Polycrystalline-silicon device technology for large-area electronics , 1986, IEEE Transactions on Electron Devices.

[2]  K. Olasupo,et al.  Leakage current mechanism in sub-micron polysilicon thin-film transistors , 1996 .

[3]  T. Sigmon,et al.  High-performance thin-film transistors fabricated using excimer laser processing and grain engineering , 1998 .

[4]  H. Kwok,et al.  High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators , 1998, IEEE Electron Device Letters.

[5]  B. Ahn,et al.  Thin-film transistors fabricated with poly-Si films crystallized at low temperature by microwave annealing , 1999 .

[6]  C. Chang,et al.  Effects of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTs , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[7]  Yong Woo Cboi,et al.  Thin-film transistors fabricated with poly-Si films crystallized at low temperature by microwave annealing , 1999, IEEE Electron Device Letters.

[8]  Min-Koo Han,et al.  A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealing , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[9]  Kow-Ming Chang,et al.  Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric , 2003 .

[10]  A. Chin,et al.  High-performance poly-silicon TFTs incorporating LaAlO/sub 3/ as the gate dielectric , 2005, IEEE Electron Device Letters.

[11]  J.C. Lee,et al.  Decoupling of cold carrier effects in hot carrier reliability of HfO2 gated nMOSFETs , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[12]  Chia-Pin Lin,et al.  High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric , 2006 .