The Optimal Decision Combination in Semiconductor Manufacturing

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In a wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers in order to improve production efficiency and satisfy customers’ demands of on-time delivery. Cycle time and average work-in-process reduction while meeting customers’ requirements play an important role in improving the competitiveness and sustainability of a semiconductor manufacturer. In this research, we propose the optimal combination rules for lot scheduling problems in wafer fabs, focusing on three complex areas of decision making: lot release control, batch sizing, and dispatching lots to enhance competitiveness and sustainability of a semiconductor facility.

[1]  Gabriel R. Bitran,et al.  Hierarchical Production Planning: A Single Stage System , 1981, Oper. Res..

[2]  Lin Danping,et al.  A review of the research methodology for the re-entrant scheduling problem , 2011 .

[3]  Hsien-Pin Hsu,et al.  The heuristic preemptive dispatching method for convey-based automated material handling system of 450 mm wafer fabrication , 2016, Comput. Ind. Eng..

[4]  Lars Mönch,et al.  Simulation-based performance assessment of master planning approaches in semiconductor manufacturing , 2014 .

[5]  Li Li,et al.  An efficient adaptive dispatching method for semiconductor wafer fabrication facility , 2016 .

[6]  Ari P. J. Vepsalainen.  Priority rules for job shops with weighted tardiness costs , 1987 .

[7]  Oliver Rose,et al.  A framework for effective shop floor control in wafer fabs , 2015, 2015 Winter Simulation Conference (WSC).

[8]  L. Li,et al.  Adaptive Dispatching Rule for Semiconductor Wafer Fabrication Facility , 2013, IEEE Transactions on Automation Science and Engineering.

[9]  Mark Stevenson,et al.  Aggregate load-oriented workload control: A review and a re-classification of a key approach , 2006 .

[10]  Lawrence M. Wein,et al.  Scheduling semiconductor wafer fabrication , 1988 .

[11]  Kai Li,et al.  SCHEDULING A SINGLE BATCH-PROCESSING MACHINE WITH NON-IDENTICAL JOB SIZES IN FUZZY ENVIRONMENT USING AN IMPROVED ANT COLONY OPTIMIZATION , 2010 .

[12]  Lee W. Schruben,et al.  Planning and scheduling in Japanese semiconductor manufacturing , 1994 .

[13]  Reha Uzsoy,et al.  Scheduling and order release in a single-stage production system , 1995 .

[14]  D. Y. Sha,et al.  A dispatching rule for photolithography scheduling with an on-line rework strategy , 2006, Comput. Ind. Eng..

[15]  Richard Bellman,et al.  Mathematical Aspects Of Scheduling And Applications , 1982 .

[16]  Zhibin Jiang,et al.  Combined scheduling algorithm for re-entrant batch-processing machines in semiconductor wafer manufacturing , 2015 .

[17]  Karl Johan Åström,et al.  Control: A perspective , 2014, Autom..

[18]  Judith E. Dayhoff,et al.  Signature analysis of dispatch schemes in wafer fabrication , 1986 .

[19]  Mauricio G. C. Resende,et al.  A scheduling rule for job release in semiconductor fabrication , 1988 .

[20]  Chun-Hung Chen,et al.  Dynamic scheduling rule selection for semiconductor wafer fabrication , 2001, Proceedings 2001 ICRA. IEEE International Conference on Robotics and Automation (Cat. No.01CH37164).

[21]  Toly Chen,et al.  Evaluating sustainable advantages in productivity with a systematic procedure , 2016 .

[22]  Yeu-Shiang Huang,et al.  A mixed dispatching rule for semiconductor wafer fabrication , 2018 .

[23]  Subhash C. Sarin,et al.  A survey of dispatching rules for operational control in wafer fabrication , 2011 .

[24]  Shu Li,et al.  Minimum inventory variability schedule with applications in semiconductor fabrication , 1996 .

[25]  Bernd Scholz-Reiter,et al.  Evolutionary generation of dispatching rule sets for complex dynamic scheduling problems , 2013 .

[26]  J. Harland,et al.  Environmental sustainability in the semiconductor industry , 2008, 2008 IEEE International Symposium on Electronics and the Environment.

[27]  Fei Qiao,et al.  Layered Drum-Buffer-Rope-Based Scheduling of Reentrant Manufacturing Systems , 2013, IEEE Transactions on Semiconductor Manufacturing.

[28]  Kwang-Min Choi,et al.  Hazard identification of powder generated from a chemical vapor deposition process in the semiconductor manufacturing industry. , 2013, Journal of occupational and environmental hygiene.

[29]  Stanley B. Gershwin,et al.  Hierarchical real-time scheduling of a semiconductor fabrication facility , 1990, Ninth IEEE/CHMT International Symposium on Electronic Manufacturing Technology,Competitive Manufacturing for the Next Decade.

[30]  Zhibin Jiang,et al.  An integrated release and dispatch policy for semiconductor wafer fabrication , 2014 .

[31]  Yung-Chia Chang,et al.  An enhanced model for SDBR in a random reentrant flow shop environment , 2014 .