Early SEU fault injection in digital, analog and mixed signal circuits: a global flow

Fault injection techniques have been proposed for years to early analyze the dependability characteristics of digital circuits. Very few attempts have however been reported to perform the same task in analog parts. Furthermore, these attempts are all based on parametric variations. With the increasing number of mixed signal circuits, a unified approach becomes mandatory to globally validate the digital and analog parts, while taking into account real faults occurring in the field, e.g. SEUs. In this paper, a global analysis flow is proposed, based on a high-level model of the circuit. The possibility to inject transient faults in the different parts is discussed. The results obtained on a case study are reported to show the feasibility of the injection in analog blocks.

[1]  Brian A. A. Antao,et al.  Behavioral modeling phase-locked loops for mixed-mode simulation , 1996 .

[2]  Régis Leveugle Fault injection in VHDL descriptions and emulation , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[3]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[4]  Pedro J. Gil,et al.  Comparison and application of different VHDL-based fault injection techniques , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[5]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Mark Zwolinski,et al.  Behavioural modelling of operational amplifier faults using VHDL-AMS , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Massimo Violante,et al.  Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[8]  Marco Ottavi,et al.  Bit flip injection in processor-based architectures: a case study , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[9]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[10]  Régis Leveugle Automatic modifications of high level VHDL descriptions for fault detection or tolerance , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[11]  Bernie Mulgrew,et al.  IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , 1998 .

[12]  Israel Koren,et al.  Reliability enhancement of analog-to-digital converters (ADCs) , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[13]  Régis Leveugle,et al.  Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments , 2003, J. Electron. Test..

[14]  Giovanni Squillero,et al.  New techniques for speeding-up fault-injection campaigns , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Resve Saleh,et al.  Simulation and analysis of transient faults in digital circuits , 1992 .

[16]  Alexandre M. Amory,et al.  Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL , 2000, IOLTW.