Concept for a 12-bit Digital Bandpass Delta-Sigma Modulator for Power Amplifier Applications

A digital bandpass delta-sigma modulator (BPDSM) with an SNR of 74 dB at a bandwidth of 20 MHz is proposed. A time-interleaved structure and optimized sparse-tree adders ensure a high sampling frequency and thus a high input signal frequency range. The concept is based on static CMOS gates using a commercial 65 nm process. Simulations indicate a sampling frequency up to 6.6 GHz and a signal frequency of up to 1.67 GHz.

[1]  Minxuan Zhang,et al.  High Performance Low-Power Sparse-Tree Binary Adders , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[2]  R. Krishnamurthy,et al.  A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  Kari Halonen,et al.  Transmitter utilising bandpass delta-sigma modulator and switching mode power amplifier , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Azita Emami-Neyestanak,et al.  Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[5]  B. Bloechel,et al.  A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[6]  Jean-François Naviner,et al.  Temporel and spectral analysis of time interleaved high pass sigma delta converter , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..