A flexible multi-channel high-resolution time-to-digital converter ASIC

A data driven multi-channel time-to-digital converter (TDC) circuit with programmable resolution (/spl sim/25 ps-800 ps binning) and a dynamic range of 102.4 /spl mu/s has been implemented in a 0.25 /spl mu/m CMOS technology. An on-chip PLL is used for clock multiplication up to 320 MHz from an external 40 MHz reference. A 32 element delay locked loop (DLL) performs time interpolation down to 97.5 ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5 ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation.

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