Hamming Based Multiple Transient Error Correction Code for NoC Interconnect

[1]  M. Vinodhini,et al.  Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect , 2018, 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[2]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[3]  Zhonghai Lu,et al.  Multi-bit transient fault control for NoC links using 2D fault coding method , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[4]  Wameedh Nazar Flayyih Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication , 2018 .

[5]  M. Vinodhini,et al.  Reliable low power NoC interconnect , 2018, Microprocess. Microsystems.

[6]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Bin Wang,et al.  Multiple continuous error correct code for high performance network-on-chip , 2011, 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics.

[8]  Cecilia Metra,et al.  Configurable Error Control Scheme for NoC Signal Integrity , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[9]  Naresh R. Shanbhag,et al.  Coding for system-on-chip networks: a unified framework , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Luca Benini,et al.  Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Yi Liu,et al.  Low power and reliable interconnection with combination of Crosstalk Avoidance Green Coding and capacitively charge-sharing transmitter for network-on-chip , 2018, Microelectron. J..

[12]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[13]  Paul Ampadu,et al.  Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[14]  Bashir M. Al-Hashimi,et al.  Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks , 2007 .

[15]  M. Vinodhini,et al.  Multi-Bit Error Correction Coding with Crosstalk Avoidance Using Parity Sharing Technique for NoC , 2018, 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS).

[16]  Kwang-Ting Cheng,et al.  End-to-end error correction and online diagnosis for on-chip networks , 2011, 2011 IEEE International Test Conference.

[17]  Sivakumar Rajagopal,et al.  An Improved Low-Power Coding for Serial Network-On-Chip Links , 2020, Circuits Syst. Signal Process..

[18]  T. Moon Error Correction Coding: Mathematical Methods and Algorithms , 2005 .