An Extended Phase Detector 2.56/3.2Gb/s Clock And Data Recovery design with Digitally Assisted Lock Detector

In the paper, a novel 2.56/3.2Gb/s full-rate phase detector is developed for integration with Clock Data Recovery (CDR) circuit in high speed SerDes applications. An Extended Phase Detector (EPD) circuit is proposed to replace the full-rate Hogge architecture. To incorporate a LC-tank voltage control oscillator with cross-coupled pair and a differential charge pump with common mode feedback. The Digitally Assisted Lock Detector (DALD) circuitry provides a timing decision for switching dual loops between phase or frequency detector in the CDR circuits. The CDR circuit is fabricated in a 0.18 ·m 1P6M Standard CMOS process in an area of 0.8µ1.0 mm2. This CDR chip exhibits a low jitter performance of 2.12 ps RMS in the recovered clock and a BER is 3.5 × 10−9 with PRBS of 231-1 sequence. The power consumption is 136mW with a 1.8V supply at 3.2Gb/s.

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