Defect diagnoses and localization methodology for pipelined ADCs

In this paper, we present a methodology to diagnose and localize the defects of pipelined analog-to-digital converters. A DFT is proposed to generate the required test stimulus and to provide the required controllability to collect the fault signature. A model is proposed to relate the fault signature to the fault type and to identify its location. Without losing the generality, the main focus of this paper is to detect and localize the capacitance mismatch and gain degradation stage-wise. The methodology could be useful for identifying the yield-loss causes and for reliability investigation.

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