Optimal design of broadband ATM switches for VLSI implementations

A new design approach, optimal design approach of ATM switches, is proposed. This approach starts with given performance requirements and calculates the switch design parameters while minimizing VLSI implementation cost. The design problems are formulated as non-linear discrete optimization problems at both the architecture level and the circuit level. At the architecture level we consider an input/output buffered switch architecture. At the circuit level we consider a high bit rate inverter chain which is based on a new GaAs logic family.<<ETX>>