Branch-and-bound placement for building block layout

We present a branch-and-bound placement technique for building block layout that effectively searches for an optimal placement in the whole solution space. We first describe a block placement problem and its solution space. Then we explain branching and bounding operations designed for the placement problem. Constraints on critical nets and/or the shape of a resulting chip can be taken into account in the search process. Experiments reveals that the number of blocks the method can manage is around six if the whole solution space is explored. For a problem which contains more blocks than the limit, we decompose the problem hierarchically and apply the method to each subproblem. The results for standard benchmark examples and a comparison with those of other systems are given to demonstrate the performance of the method.

[1]  Carl Sechen Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[2]  Chak-Kuen Wong,et al.  An algorithm for optimal two-dimensional compaction of VLSI layouts , 1983, Integr..

[3]  Hiroyuki Watanabe,et al.  Graph-Optimization Techniques for IC Layout and Compaction , 1983, 20th Design Automation Conference Proceedings.

[4]  Ravi Nair,et al.  Generation of performance constraints for layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  C. L. Liu,et al.  A New Algorithm for Floorplan Design , 1986, DAC 1986.

[6]  Bryan Preas,et al.  Placement Algorithms for Arbitrarily Shaped Blocks , 1979, 16th Design Automation Conference.

[7]  R. Otten Automatic Floorplan Design , 1982, DAC 1982.

[8]  Michael Upton,et al.  Integrated placement for mixed macro cell and standard cell designs , 1990, 27th ACM/IEEE Design Automation Conference.

[9]  H. Onodera,et al.  Step by step placement strategies for building block layout , 1989, IEEE International Symposium on Circuits and Systems,.

[10]  Hidetoshi Onodera,et al.  Branch-and-Bound Placement for Building Block Layout , 1993 .

[11]  D. A. Mlynski,et al.  A Combined Force and Cut Algorithm for Hierarchical VLSI Layout , 1982, DAC 1982.

[12]  Ernest S. Kuh,et al.  Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Wayne Wei-Ming Dai,et al.  Hierarchical placement and floorplanning in BEAR , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[15]  Bryan D. Ackland,et al.  Physical Design Automation of Vlsi Systems , 1988 .