Multiple Bus Architectures

A recent study noted that for shared memory multiprocessors the single system bus typically used to connect the processor to the memory is by far the most limiting resource, and system performance can be increased considerably by increasing the capacity of the bus. One way of increasing the bus capacity, and also the system's reliability and fault tolerance, is to increase the number of buses. In this article the authors discuss using multiple buses to provide highbandwidth connections between the processors and the shared memory, thereby allowing the construction of larger and more powerful systems than currently possible.

[1]  Chita R. Das,et al.  Bandwidth availability of multiple-bus multiprocessors , 1985, IEEE Transactions on Computers.

[2]  Marco Ajmone Marsan,et al.  Modeling Bus Contention and Memory Interference in a Multiprocessor System , 1983, IEEE Transactions on Computers.

[3]  Donald F. Towsley,et al.  Approximate Models of Multiple Bus Multiprocessor Systems , 1986, IEEE Transactions on Computers.

[4]  Trevor N. Mudge,et al.  A semi-Markov model for the performance of multiple-bus systems , 1985, IEEE Transactions on Computers.

[5]  Alan Jay Smith,et al.  Cache evaluation and the impact of workload choice , 1985, ISCA '85.

[6]  Tilak Agerwala,et al.  Performance Analysis of Future Shared Storage Systems , 1984, IBM J. Res. Dev..

[7]  James K. Archibald,et al.  Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.

[8]  CORNELIS H. HOOGENDOORN A General Model for Memory Interference in Multiprocessors , 1977, IEEE Transactions on Computers.

[9]  Keki B. Irani,et al.  A Markovian Queueing Network Model for Performance Evaluation of Bus-Deficient Multiprocessor Systems , 1983, ICPP.

[10]  Mateo Valero,et al.  Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors , 1982, IEEE Transactions on Computers.

[11]  John P. Hayes,et al.  Analysis of Multiple-Bus Interconnection Networks , 1986, J. Parallel Distributed Comput..

[12]  William Daniel Strecker An analysis of the instruction execution rate in certain computer structures , 1970 .

[13]  Warren D. Little,et al.  Asynchronous Arbiter Module , 1975, IEEE Transactions on Computers.

[14]  Mateo Valero,et al.  M-users B-servers arbiter for multiple-busses multiprocessors , 1982 .

[15]  Mateo Valero,et al.  A performance evaluation of the multiple bus network for multiprocessor systems , 1983, SIGMETRICS '83.