Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOx interlayer between SiO2 and HfO2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

[1]  E. H. Nicollian,et al.  Mos (Metal Oxide Semiconductor) Physics and Technology , 1982 .

[2]  Anabela Veloso,et al.  Significant reduction of Positive Bias Temperature Instability in high-k/metal-gate nFETs by incorporation of rare earth metals , 2009 .

[3]  Mark Bohr,et al.  The evolution of scaling from the homogeneous era to the heterogeneous era , 2011, 2011 International Electron Devices Meeting.

[4]  E. Cartier,et al.  Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling , 2011, 2011 International Electron Devices Meeting.

[5]  Aaron Thean,et al.  Analytical model for anomalous Positive Bias Temperature Instability in La-based HfO2 nFETs based on independent characterization of charging components , 2013 .

[6]  B. Kaczer,et al.  SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI , 2013, IEEE Transactions on Electron Devices.

[7]  S. Chew,et al.  Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[8]  Guidelines for reducing NBTI based on its correlation with effective work function studied by CV-BTI on high-k first MOS capacitors with slant-etched SiO2 , 2014, 2014 IEEE International Reliability Physics Symposium.

[9]  L. Witters,et al.  Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[10]  O. Faynot,et al.  3DVLSI with CoolCube process: An alternative path to scaling , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[11]  N. Horiguchi,et al.  Zero-thickness multi work function solutions for N7 bulk FinFETs , 2016, 2016 IEEE Symposium on VLSI Technology.

[12]  T. Schram,et al.  Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole , 2016, 2016 IEEE Symposium on VLSI Technology.

[13]  K. Wostyn,et al.  Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[14]  Barry P. Linder,et al.  Process optimizations for NBTI/PBTI for future replacement metal gate technologies , 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

[15]  Dimitri Linten,et al.  BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

[16]  Impact of low thermal processes on reliability of high-k/metal gate stacks , 2017 .