Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS
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A. Chasin | N. Horiguchi | N. Collaert | D. Linten | L. Ragnarsson | B. Kaczer | L. Witters | H. Arimura | J. Franco | S. Sioncke | A. Vandooren | A. Vais | V. Putcha | Q. Xie | M. Givens | F. Tang | X. Jiang | A. Subirats
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