Experimental performance analysis of a CMOS amplifier considering different layout techniques

In order to obtain high-performance systems on chip (SoC) using complementary metal oxide semiconductor (CMOS) technology is necessary to increase the robustness and decrease the delay, power consumption, and surface area of the integrated circuits. We present an experimental performance analysis of a class AB CMOS amplifier designed with different layout techniques (serpentine, concentric, and interdigitated). These layout techniques are evaluated in function of product potency delay area and amplifier characteristics such as electrical gain, common mode rejection ratio, power supply rejection ratio, offset, and slew rate. Based on the experimental performance results of the class AB CMOS amplifier, serpentine technique reduces its surface area to 64 %, and decreases the power consumption close to 39 % with respect to the conventional technique. In the SoC design, serpentine layout technique could be used to improve the electrical performance of their CMOS amplifiers.

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