Systematic design for manufacturability ( DfM ) scheme including triple gates for hot spot elimination under the low-k1 lithography condition is proposed and efficient approaches to the hot spot elimination at each development stage in the DfM scheme are discussed in view of the actual situation under the concurrent development of design rule ( DR ), layout, process, optical proximity correction ( OPC ) and resolution enhancement technique ( RET ) technologies. Integrated-type lithography simulation system with OPC tool is much available for the fast processing at the initial stage and promising to be complementarily used for the verification of chip-level layout with conventional-type one at the final development stage. Low order of the lithography empirical model originating moderate prediction accuracy for all kinds of patterns is hopeful to be used at the initial development stage because it is difficult to obtain a lot of reliable experimental data for making the accurate empirical lithography model due to frequent improvement of the process, OPC and RET technologies. At the final development stage, sufficient and reliable experimental data for device pattern variations allow us to implement the higher order of the empirical model. The DfM scheme with efficient approaches in view of the actual situation under the concurrent development is found to be promising for the robust pattern formation under the low-k1 lithography condition.