Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole

As semiconductor industry reached nanotechnology generation and consumer electronics era, the competition is no longer among individual semiconductor companies. Indeed, the collaborations among horizontally specialized value providers are critical for the success of the companies as well as the whole ecosystem. This paper aims to propose a novel index, i.e., Overall Wafer Effectiveness (OWE), to measure wafer productivity and drive various improvement directions for semiconductor ecosystem as a whole. Furthermore, the proposed OWE can be easily extended to incorporate additional attributes such as mask-field-utilization, throughput, and yield for effective management. We conducted a number of case studies in real settings. The results have shown that OWE can be employed as a semiconductor industry standard to drive collaborative efforts among IC designers, equipment vendors, and manufacturers in the ecosystem to enhance total wafer effectiveness. This paper concludes with discussions on value propositions of proposed OWE indices and future research directions.

[1]  G. A. Allan,et al.  A yield improvement technique for IC layout using local design rules , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Costas J. Spanos,et al.  Semiconductor yield improvement: results and best practices , 1995 .

[3]  Chen-Fu Chien,et al.  An iterative cutting procedure for determining the optimal wafer exposure pattern , 1999 .

[4]  Chen-Fu Chien,et al.  Analyzing repair decisions in the site imbalance problem of semiconductor test machines , 2003 .

[5]  Chen-Fu Chien,et al.  Constructing the OGE for promoting tool group productivity in semiconductor manufacturing , 2007 .

[6]  J.S. Pettinato,et al.  Technology decisions to minimize 450-mm wafer size transition risk , 2005, IEEE Transactions on Semiconductor Manufacturing.

[7]  Christopher A. Bode,et al.  Run-to-run control and performance monitoring of overlay in semiconductor manufacturing , 2002 .

[8]  A. Ferris-Prabhu.  An algebraic expression to count the number of chips on a wafer , 1989, IEEE Circuits and Devices Magazine.

[9]  James Moyne,et al.  Run-to-Run Control in Semiconductor Manufacturing , 2000 .

[10]  Chen-Fu Chien,et al.  Using genetic algorithms (GA) and a coloured timed Petri net (CTPN) for modelling the optimization-based schedule generator of a generic production scheduling system , 2007 .

[11]  Chen-Fu Chien,et al.  A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing , 2006, J. Intell. Manuf..

[12]  D. K. de Vries,et al.  Investigation of gross die per wafer formulas , 2005 .

[13]  John E. Beasley,et al.  Algorithms for Unconstrained Two-Dimensional Guillotine Cutting , 1985 .

[14]  A.J. de Ron,et al.  Equipment effectiveness: OEE revisited , 2005, IEEE Transactions on Semiconductor Manufacturing.

[15]  Charles H. Fine.  CLOCKSPEED‐BASED STRATEGIES FOR SUPPLY CHAIN DESIGN1 , 2009 .

[16]  Chen-Fu Chien,et al.  Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing , 2003 .

[17]  Chen-Fu Chien,et al.  Manufacturing Intelligence to Exploit the Value of Production and Tool Data to Reduce Cycle Time , 2011, IEEE Transactions on Automation Science and Engineering.

[18]  Chen-Fu Chien,et al.  Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing , 2007, International Journal of Production Economics.

[19]  J. F. Moore,et al.  Predators and prey: a new ecology of competition. , 1993, Harvard business review.

[20]  Chen-Fu Chien,et al.  Economic analysis of 450mm wafer migration , 2007, 2007 International Symposium on Semiconductor Manufacturing.

[21]  Samuel H. Huang,et al.  Overall throughput effectiveness (OTE) metric for factory-level performance monitoring and bottleneck detection , 2007 .

[22]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[23]  Jung-Hoon Chun,et al.  Extrusion spin coating: an efficient and deterministic photoresist coating method in microlithography , 2004, IEEE Transactions on Semiconductor Manufacturing.

[24]  Jamil Kawa,et al.  Design for Manufacturability and Yield for Nano-Scale CMOS , 2007, Series on Integrated Circuits and Systems.

[25]  Shengwei Ding,et al.  Economic Efficiency Analysis of Wafer Fabrication , 2007, IEEE Transactions on Automation Science and Engineering.

[26]  Chen-Fu Chien,et al.  Beyond make-or-buy: cross-company short-term capacity backup in semiconductor industry ecosystem , 2013 .

[27]  Chen-Fu Chien,et al.  Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product life cycle , 2010 .

[28]  Robert C. Leachman.  Closed-loop measurement of equipment efficiency and equipment capacity , 1997 .

[29]  John W. Fowler,et al.  A new scheduling approach using combined dispatching criteria in wafer fabs , 2003 .

[30]  Chen-Fu Chien,et al.  A cutting algorithm for optimizing the wafer exposure pattern , 2001 .

[31]  Mhand Hifi,et al.  The DH/KD algorithm: a hybrid approach for unconstrained two-dimensional cutting problems , 1997 .