Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis
暂无分享,去创建一个
[1] D. Avis. A Revised Implementation of the Reverse Search Vertex Enumeration Algorithm , 2000 .
[2] Wayne H. Wolf. The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..
[3] G. Ziegler,et al. Polytopes : combinatorics and computation , 2000 .
[4] Lothar Thiele,et al. Influence of different system abstractions on the performance analysis of distributed real-time systems , 2007, EMSOFT '07.
[5] Lothar Thiele,et al. Complex task activation schemes in system level performance analysis , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[6] Lothar Thiele,et al. Resource constrained scheduling of uniform algorithms , 1993, J. VLSI Signal Process..
[7] L. Thiele,et al. Performance analysis of multiprocessor DSPs: a stream-oriented component model , 2005, IEEE Signal Processing Magazine.
[8] Nikil D. Dutt,et al. Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors , 2001, IEEE Des. Test Comput..
[9] Luca Benini,et al. SystemC Cosimulation and Emulation of Multiprocessor SoC Designs , 2003, Computer.
[10] Jürgen Teich,et al. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications , 2008, ARC.
[11] B. Ramakrishna Rau,et al. Efficient design space exploration in PICO , 2000, CASES '00.
[12] Andy D. Pimentel,et al. A systematic approach to exploring embedded system architectures at multiple abstraction levels , 2006, IEEE Transactions on Computers.
[13] William Fornaciari,et al. An area estimation methodology for FPGA based designs at systemc-level , 2004, Proceedings. 41st Design Automation Conference, 2004..