A 100MHz, 8mW ROM–less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using ROM lookup table to store the sine values. ROM elimination has resulted in significant power and area savings. The proposed DDFS has been implemented using 0.5µm CMOS process and occupies 1.4mm2area. It achieves an extremely low power consumption of only 8mW at 100MHz and operates from a single 2.7V supply. The SFDR is better than 58dBc at low synthesized frequencies and the frequency resolution is 1.5kHz.

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