论文信息 - Area-efficient and self-biased capacitor multiplier for on-chip loop filter

Area-efficient and self-biased capacitor multiplier for on-chip loop filter

A self-biased capacitor multiplier is proposed to reduce the area of a large integrating capacitor in loop filters. A prototype Sigma-Delta fractional-N frequency synthesiser including the capacitor multiplier is fabricated with a 0.35 mum BiCMOS process. The designed capacitor multiplier makes capacitance of 2.72 nF from an on-chip capacitor of 170 pF with current consumption of 240 muA at 2.8 V. The frequency synthesiser demonstrates the in-band phase noise of -79 dBc/Hz at 5 kHz offset

In-Chul Hwang | In-Chul Hwang

[1] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[2] Xiaoyang Zeng,et al. Compact current-mode loop filter for PLL applications , 2005 .

[3] M. Steyaert,et al. A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[4] Mohammed Ismail,et al. Adaptive Miller capacitor multiplier for compact on-chip PLL filter , 2003 .

[5] Edgar Sanchez-Sinencio,et al. A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier , 2003, IEEE J. Solid State Circuits.