Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications
暂无分享,去创建一个
[1] K. Higuchi,et al. Investigation of Verify-Programming Methods to Achieve 10 Million Cycles for 50nm HfO2 ReRAM , 2012, 2012 4th IEEE International Memory Workshop.
[2] Ken Takeuchi,et al. x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression , 2012, 2012 Symposium on VLSI Circuits (VLSIC).
[3] Shuhei Tanakamaru,et al. Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.
[4] Shuhei Tanakamaru,et al. 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm , 2011, 2011 IEEE International Solid-State Circuits Conference.