Slew-down: analysis of slew relaxation for low-impact clock buffers
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[1] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[2] Yu Cao,et al. Exploring sub-20nm FinFET design with Predictive Technology Models , 2012, DAC Design Automation Conference 2012.
[3] Majid Sarrafzadeh,et al. Minimal buffer insertion in clock trees with skew and slew rate constraints , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Chandramouli V. Kashyap,et al. Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Chung-Kuan Cheng,et al. Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .
[6] Marek Patyra,et al. Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Andrew B. Kahng,et al. Zero-skew clock routing trees with minimum wirelength , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.
[8] Baris Taskin,et al. FinFET-Based Low-Swing Clocking , 2015, ACM J. Emerg. Technol. Comput. Syst..
[9] Baris Taskin,et al. Timing characterization of clock buffers for clock tree synthesis , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).