A Timing-Driven Global Router for Symmetrical Array Based FPGAs
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In this paper, we present a timing-driven global router for symmetrical array-based architecture FPGAs. The routing resources in symmetrical array based FPGAs consist of segments of various lengths. The timing constraints are specified as delay bounds on source-sink pairs of nets. The algorithm proceeds in a hierarchical top-down manner and is able to utilize various routing segments with global consideration in order to meet the timing constraints. Furthermore, the algorithm can be extended to perform detailed routing simultaneously with global routing. Experimental results on real circuits show that the algorithm is promising in satisfying the timing constraints compared with the conventional global router. The theory of powerlists was recently introduced by Jay Misra. It gives us the ability to specify and verify certain parallel algorithms and connection structures. The notation is similar to sequential functional programming languages (such as Miranda [Tur86]) but with constructs for expressing balanced division of lists. In the first part of this work we study how some known algorithms for the hypercube can be specified succinctly in the powerlist notation. These specifications can then be verified quite succinctly in comparison to the original proofs of the algorithms. The second part of this work is to study how algorithms written in the powerlist notation can be mapped efficiently onto the hypercube. It turns out that many algorithms have a mapping to the hypercube that is as efficient as mappings to architectures that have all to all connections. This mapping is known in the literature as the Gray code. Operators on these Gray coded powerlists can be implemented efficiently on a hypercube. Algebraically the Gray coding is an isomorphism between powerlists expressions and their Gray coded equivalents.