Workload-driven floorplanning for MIPS optimization

An approach to early floorplanning in which optimization of a CPU chip floorplan is done in the context of a program benchmark (workload) is presented. The methodology integrates workload-driven cycles-per-instruction estimation into the traditional cycle-time evaluation process implied by an (early) floorplanning tool. This effectively adds an extra dimension to the floorplanning optimization cost function and search space, allowing superior MIPS-tuning of the VLSI chip.<<ETX>>

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