A light-weight energy-efficient resilient circuit for variation tolerance

“In-situ” error detection and correction (EDAC) techniques have been proposed to reduce PVTA margins and improve energy efficiency. However, previous EDAC works incur large design complexity and overhead. In this paper, we propose a light-weight energy-efficient latch transition sensor(LTS) that adds only 12 transistors to a conventional latch. It uses a two-way monitor that senses data transitions within detection window to indicate timing errors. It has low hardware overhead and increases energy efficiency. LTS is implemented in a commercial processor at SMIC 40nm process with a energy saving of 34.55%, while incurring 9.33% system area overhead compared to a baseline design. At 0.6v, the LTS processor gains 6.89% performance increasing at fixed voltage, 2%∼7% energy saving at fixed throughput and 1%∼3% less area overhead than other error-resilient processors using previous EDAC techniques.