High precision result evaluation of VLSI
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Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.
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