Design Of 3 bit synchronous Counter using DLDFF

Flip flops are the fundamental building blocks for all sequential circuits. Data transition look ahead D flip flop consumes less power than the conventional D Flip flop. The power consumption of CMOS LSI’s is a very important issue these days. Here we propose a modified data transition D flip flop which consumes less power than existing data transition D flip flop. The total power reduction of proposed data transition D flip flop is 18.37% when compared with existing data transition D flip flop. We design a 3 bit synchronous counter which consumes less power than existing data transition look ahead D flip flop and D flip flop.