UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction
暂无分享,去创建一个
Shianling Wu | Xiaoqing Wen | Boryau Sheu | Shyh-Horng Lin | Laung-Terng Wang | Khader S. Abdel-Hafez | Ming-Tung Chang
[1] Janak H. Patel,et al. Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[2] Nur A. Touba,et al. Virtual scan chains: a means for reducing scan length in cores , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[3] Kuen-Jong Lee,et al. Broadcasting test patterns to multiple circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Minesh B. Amin,et al. X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[5] B. Koenemann. LFSR-coded test patterns for scan designs , 1991 .
[6] Janusz Rajski,et al. Test Data Decompression for Multiple Scan Designs with Boundary Scan , 1998, IEEE Trans. Computers.
[7] Bernard Courtois,et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.
[8] Hans-Joachim Wunderlich,et al. Tailoring ATPG for embedded testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[9] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[10] Shianling Wu,et al. VirtualScan: a new compressed scan technology for test cost reduction , 2004 .
[11] Kozo Kinoshita,et al. On low-capture-power test generation for scan testing , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[12] Shianling Wu,et al. At-speed logic BIST for IP cores , 2005, Design, Automation and Test in Europe.
[13] Nilanjan Mukherjee,et al. Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.
[14] Alex Orailoglu,et al. Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[15] Janak H. Patel,et al. A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[16] Brion L. Keller,et al. OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).