An efficient hardware-software codesign of 3D rasterization module

This paper proposes a hardware-software codesign of rasterization, which is the most complex fixed function of the programmable three-dimensional (3D) graphics rendering flow. Our approach first develops a software code executed by the existed programmable shader core to implement the setup function of rasterization module. Next, a special scan-conversion acceleration unit is developed to cooperate with the shader core to interpolate the required data attributes together. We implement the scan-conversion function in fixed-point domain such that it only costs 8.5k gates, about 1.7% of the entire graphics processor unit (GPU) gate count, but can help reducing more than 30% cycles compared with the pure software implementation. Since our design realizes the rasterization in the shader core, it can avoid the cycles spent on transferring the interpolated data between different storage units in some GPU designs which adopt hardware rasterization designs. The proposed rasterization design is very suitable for low-cost embedded graphics applications.