High performance low Vcc operation by hiding repair information access latency

Bit errors in SRAM are one of the most critical problems in reducing supply voltage. Existing methods to address this problem share a common issue of additional latency in SRAM access for error correction or data repair. The additional latency increases clock period thereby losing opportunities of further reduction in supply voltage. In this paper, we propose an architectural retiming to hide the additional latency for data repair. It reduces clock period (typically determined by the memory access stage at low supply voltage) by moving the function of data repair information access from the memory access stage to an earlier pipe stage. Our case study with an existing CPU core design shows that the proposed method offers up to 42% higher operating frequency at 0.6V.

[1]  Anantha Chandrakasan,et al.  A 28nm 0.6V low-power DSP for mobile applications , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  Amin Ansari,et al.  Enabling ultra low voltage system operation by tolerating on-chip cache failures , 2009, ISLPED.

[3]  Saurabh Dighe,et al.  A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Ramy E. Aly,et al.  A Family of 32 nm IA Processors , 2011, IEEE Journal of Solid-State Circuits.

[5]  Avesta Sasan,et al.  A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache) , 2009, CASES '09.

[6]  Kaushik Roy,et al.  A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[7]  Nikil D. Dutt,et al.  FFT-Cache: A Flexible Fault-Tolerant Cache architecture for ultra low voltage operation , 2011, 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

[8]  Alaa R. Alameldeen,et al.  Trading off Cache Capacity for Reliability to Enable Low Voltage Operation , 2008, 2008 International Symposium on Computer Architecture.

[9]  Trevor Mudge,et al.  On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology , 2007 .

[10]  Amin Ansari,et al.  Archipelago: A polymorphic cache design for enabling robust near-threshold operation , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.