A Spill Code Placement Framework for Code Scheduling
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Naohiro Ishii | Yuji Iwahori | Tatsuya Hayashi | Dingchao Li | N. Ishii | Y. Iwahori | Tatsuya Hayashi | Dingchao Li
[1] Eduardo B. Fernández,et al. Bounds on the Number of Processors and Time for Multiprocessor Optimal Schedules , 1973, IEEE Transactions on Computers.
[2] Keith D. Cooper,et al. Improvements to graph coloring register allocation , 1994, TOPL.
[3] C. Norris,et al. A schedular-sensitive global register allocator , 1993, Supercomputing '93.
[4] Balas K. Natarajan,et al. Spill-free parallel scheduling of basic blocks , 1995, MICRO 1995.
[5] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[6] John C. Gyllenhaal,et al. Code scheduling for VLIW/superscalar processors with limited register files , 1992, MICRO 1992.
[7] Jian Wang,et al. Software pipelining with register allocation and spilling , 1994, MICRO 27.
[8] Shlomit S. Pinter,et al. Register allocation with instruction scheduling , 1993, PLDI '93.
[9] Josep Llosa,et al. Heuristics for register-constrained software pipelining , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.
[10] Susan J. Eggers,et al. Integrating register allocation and instruction scheduling for RISCs , 1991, ASPLOS IV.
[11] Ron Y. Pinter,et al. Spill code minimization techniques for optimizing compliers , 1989, PLDI '89.
[12] Shlomit S. Pinter,et al. Register allocation with instruction scheduling: a new approach , 1996, Journal of Programming Languages.
[13] John R. Gurd,et al. Self-regulation of workload in the Manchester Data-Flow computer , 1995, MICRO 1995.
[14] Daniel Gajski,et al. Hypertool: A Programming Aid for Message-Passing Systems , 1990, IEEE Trans. Parallel Distributed Syst..
[15] John R. Ellis,et al. Bulldog: A Compiler for VLIW Architectures , 1986 .