A memory efficient 3-D DWT architecture

This paper proposes a memory efficient real-time 3-D DWT algorithm and its architectural implementation. As the running 3D-DWT refreshes the wavelet coefficients with the arrival of every two new frames, the latency of the conventional 3D-DWT reduces by at least 1/4 times. For realization of the transform canonical signed digit multiplier has been used. Parallelism being an added advantage for fast processing has been used with three pipelined stages in this architecture. For coefficient mapping, correlation between LPF and HPF in orthogonal Daubechies wavelet filter has been used. In this design the memory requirement has been optimized to the order O(KN/sup 2/ + (K - 2) /spl times/ N). The proposed architecture has been implemented on Xilinx FPGA devices at an operating frequency of 75 MHz. This low complexity architecture ensures 100% hardware utilization.

[1]  Magdy Bayoumi,et al.  A low power 3-D discrete wavelet transform processor for medical applications , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[2]  William A. Pearlman,et al.  An embedded wavelet video coder using three-dimensional set partitioning in hierarchical trees (SPIHT) , 1997, Proceedings DCC '97. Data Compression Conference.

[3]  Zixiang Xiong,et al.  Low bit-rate scalable video coding with 3-D set partitioning in hierarchical trees (3-D SPIHT) , 2000, IEEE Trans. Circuits Syst. Video Technol..

[4]  Swapna Banerjee,et al.  A CORDIC based array architecture for complex discrete wavelet transform , 2001, GLSVLSI '01.

[5]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[6]  Wael Badawy,et al.  A low power prototype for a 3D discrete wavelet transform processor , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  T. C. Denk,et al.  VLSI architectures for lattice structure based orthonormal discrete wavelet transforms , 1997 .

[8]  S. Banerjee,et al.  Unified CORDIC-based chip to realise DFT/DHT/DCT/DST , 2002 .

[9]  Liang-Gee Chen,et al.  An efficient architecture for two-dimensional discrete wavelet transform , 2001, IEEE Trans. Circuits Syst. Video Technol..

[10]  Hamid Gharavi,et al.  Subband coding algorithms for video applications: videophone to HDTV-conferencing , 1991, IEEE Trans. Circuits Syst. Video Technol..

[11]  F. Marino.  Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform , 2000 .

[12]  Jens-Rainer Ohm,et al.  Three-dimensional subband coding with motion compensation , 1994, IEEE Trans. Image Process..

[13]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[14]  Swapna Banerjee,et al.  VLSI architecture for a new real-time 3D wavelet transform , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[15]  Avideh Zakhor,et al.  Multirate 3-D subband coding of video , 1994, IEEE Trans. Image Process..

[16]  Sanjit K. Mitra,et al.  Subband DCT: definition, analysis, and applications , 1996, IEEE Trans. Circuits Syst. Video Technol..

[17]  Jens-Rainer Ohm,et al.  Advanced packet-video coding based on layered VQ and SBC techniques , 1993, IEEE Trans. Circuits Syst. Video Technol..

[18]  King Ngi Ngan,et al.  Very low bit rate video coding using 3D subband approach , 1994, IEEE Trans. Circuits Syst. Video Technol..