An optimal design for 0.1 micrometer PMOS, consistent with SIA-NTRS Roadmap projections, is developed using a Response Surface methodology (RSM). The impact of four different low thermal budget growth and deposition gate dielectric processes (Furnace oxidation, Rapid Thermal Oxidation (RTO), Rapid Thermal CVD (RTCVD) and Remote Plasma Enhanced CVD (RPECVD) on the design optimization is examined. A Design Of Experiments (DOE) approach was independently employed in each case with simulated baseline surface channel PMOSFET structures having a 2.0 nm gate oxide to statistically explore the channel and extension junction parameter spaces. Channel and extension junction parameters were separately optimized, with channel optimization performed for both doubly-implanted and uniformly doped channels. The condition for constrained optimization was the maximization of Isat at the NTRS Roadmap specified Ioff value of 3 nA/micrometer. A 20% manufacturing tolerance in channel length was factored into the optimization strategy by measuring both Isat and Ioff under their respective worst case tolerance conditions. Optimal designs with modestly differing implant specifications but exhibiting largely comparable performance characteristics were identified for each gate stack. Excellent current drivability of 279 (mu) A/micrometer was obtained at the nominal Leff of 70 nm. Optimized doubly-implanted channels provide 7.5% higher current than the uniformly doped ones. Optimum extension junction design was achieved by a high surface concentration of 2 X 1020 cm-3, extension depth of 32 nm and spacer width of 49 nm, and the analysis clearly revealed that a necessary condition for junction optimization was the onset of drain decoupling from the channel.
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