Active Through-Silicon Interposer Based 2.5D IC Design, Fabrication, Assembly and Test

Active Through-Silicon Interposer (ATSI) based 2.5D/3D IC packaging is a solution to extend Moore's law beyond the limitations inherent in 2D packages. We present the implementation of an ATSI platform for providing Analog to Digital converter (ADC), Digital to Analog converter (DAC) and embedded Power Management Unit (ePMU) functions to support high performance logic, fabrication of 140 micron pitch Via-Last Through-Silicon Via (TSV) of 40 micron height, assembly of Chip-on-Chip-on Substrate, functional test and reliability assessment. The active interposer fabricated in 130nm CMOS easily supports the I/O, Analog, Electro Static Discharge (ESD), De-cap functions with via-last TSV. This approach enables significant die-size reduction of the top die (usually in expensive 16nm CMOS or below tech. node) to achieve system miniaturization and cost reduction

[1]  G. Beyer,et al.  Interposer technology for high band width interconnect applications , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[2]  Mirko Scholz,et al.  System Level ESD Protection , 2014 .

[3]  Yuan Xie,et al.  Cost-effective design of scalable high-performance systems using active and passive interposers , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Joungho Kim.  Active Si interposer for 3D IC integrations , 2015, 2015 International 3D Systems Integration Conference (3DIC).

[5]  D. Pinjala,et al.  3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[6]  Anthony Collins,et al.  A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters , 2014, IEEE Journal of Solid-State Circuits.

[7]  Xiaowu Zhang,et al.  Heterogeneous 2.5D integration on through silicon interposer , 2015 .

[8]  Subramanian S. Iyer,et al.  Heterogeneous Integration for Performance and Scaling , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[9]  Eric Beyne,et al.  ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package , 2015, 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[10]  E. Beyne,et al.  Active-lite interposer for 2.5 & 3D integration , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).