Design and implementation of a 5-bit flash ADC for education

The DSP (Digital Signal Processing) has many advantages over the analog processing. Therefore, with the recent advent of technology most of the signal processing tasks have been transferred from the analog to the digital domain. The ADCs (Analog to Digital Converter) provide a liaison between the real world analog signals and the digital processors. Therefore, ADCs become an elementary part of almost all modern electronic systems. This work focuses on the development of a simple Flash ADC for students demonstration purpose. In this context, a 5-Bit Flash ADC is implemented. Being designed for illustration purpose, the ADC has easily accessible inputs and outputs to each module. In order to keep the system cost effective with an ease of reimplementation. The low cost and easily market available discrete analog components are employed. The digital part is kept configurable with the help of a FPGA (Field Programmable Gate Array) based implementation. The digital circuit implementation is done via Verilog, a HDL (Hardware Description Language). The system implementation is described. Testing results are also presented. These results assure a proper functionality of the designed ADC.

[1]  Arthur H. M. van Roermund,et al.  A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Stephen H. Lewis,et al.  Iterative Gain Enhancement in an Algorithmic ADC , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Saeed Mian Qaisar,et al.  An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform , 2008, J. Electr. Comput. Eng..

[4]  Stephen A. Dyer,et al.  Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[5]  Saeed Mian Qaisar,et al.  Computationally efficient adaptive rate sampling and filtering , 2007, 2007 15th European Signal Processing Conference.

[6]  Y. Ogushi,et al.  [Analog-digital conversion]. , 1973, Kokyu to junkan. Respiration & circulation.

[7]  Ian Galton,et al.  A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB , 2013, IEEE Journal of Solid-State Circuits.

[8]  Emmanuel Ifeachor,et al.  Digital Signal Processing: A Practical Approach , 1993 .

[9]  Saeed Mian Qaisar,et al.  Adaptive rate filtering a computationally efficient signal processing approach , 2014, Signal Process..

[10]  Saeed Mian Qaisar,et al.  An efficient signal acquisition with an adaptive rate A/D conversion , 2013, 2013 IEEE International Conference on Circuits and Systems (ICCAS).

[11]  Takumi Danjo,et al.  A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS , 2014, IEEE Journal of Solid-State Circuits.