Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ

Nonvolatile flip-flop (NVFF) using spin-transfer torque magnetic tunnel junctions (STT-MTJs) has been proposed to enable fine-grain power gating systems. However, the STT-MTJ-based NVFF (STT-NVFF) may not perform fast backup and disturb-free restore operations. We propose a new NVFF using complementary polarizer MTJ (CPMTJ) to alleviate these limitations. Our proposed NVFF exploits the CPMTJ structure for fast- and low-energy backup operation. The estimated backup delay is less than 10 ns in 7-nm node FinFET technology with CPMTJ size of $12\,\,\text {nm} \,\,\times $ 33 nm in a rectangular shape. Furthermore, during the restore operation, CPMTJ provides guaranteed disturb-free sensing, since the disturb torque from the two complementary pinned layers of CPMTJ cancels each other. The simulation results show >2 times improvement in the backup delay with higher restore-disturb margin compared with STT-NVFF.

[1]  V. Kursun,et al.  Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs , 2008, IEEE Transactions on Electron Devices.

[2]  Yu Cao,et al.  Exploring sub-20nm FinFET design with Predictive Technology Models , 2012, DAC Design Automation Conference 2012.

[3]  Naoki Kasai,et al.  Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs , 2009, IEEE J. Solid State Circuits.

[4]  N. Collaert,et al.  Layout density analysis of FinFETs , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

[5]  Takahiro Hanyu,et al.  Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver , 2015 .

[6]  Kaushik Roy,et al.  High-performance low-energy STT MRAM based on balanced write scheme , 2012, ISLPED '12.

[7]  Seung H. Kang,et al.  A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[8]  Mark C. Johnson,et al.  Leakage control with efficient use of transistor stacks in single threshold CMOS , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[9]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[10]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .

[11]  Kaushik Roy,et al.  Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective , 2014, IEEE Transactions on Magnetics.

[12]  Xuanyao Fong,et al.  SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture , 2014, IEEE Electron Device Letters.

[13]  Shuu'ichirou Yamamoto,et al.  Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture and Its Power-Gating Applications , 2010 .

[14]  Fabrizio Lombardi,et al.  On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  L.T. Clark,et al.  Reverse-body bias and supply collapse for low effective standby power , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  S. Kumar,et al.  Impact of Self-Heating on Reliability of a Spin-Torque-Transfer RAM Cell , 2012, IEEE Transactions on Electron Devices.

[17]  Satoshi Shigematsu,et al.  A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.

[18]  Seong-Ook Jung,et al.  A comparative study of STT-MTJ based non-volatile flip-flops , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).